1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly relates to a semiconductor device including a clock generating circuit, such as a DLL (Delay Locked Loop) circuit, that generates an internal clock.
2. Description of Related Art
In recent years, a synchronous memory device that performs an operation in synchronization with a clock has been widely used as a main memory for a personal computer or the like. In particular, in a synchronous memory device of DDR (Double Data Rate) type among various types of synchronous memories, a DLL circuit that generates an internal clock synchronized with an external clock is an essential component because it is necessary to synchronize input/output data with the external clock in a precise manner (see Japanese Patent Application Laid-open No. 2008-217947). Therefore, at least at the time of a read operation, the phase of the internal clock is strictly controlled by the DLL circuit.
However, power consumption of the DLL circuit increases as the phase control of an internal clock becomes more precise. Therefore, in the case that stricter phase control is required, it can cause a problem that the power consumption by the DLL circuit increases by the same level.
Meanwhile, because the internal clock generated by the DLL circuit is used for defining an output timing of read data, it is safe to say that generation of the internal clock is not necessary in a period other than the time of a read operation. However, once the DLL circuit is suspended, it takes a relatively long time until an internal clock that is precisely phase-controlled is generated after the DLL circuit is reactivated. Therefore, it is not realistic to suspend the DLL circuit every time the read operation is finished.
Furthermore, there are some semiconductor devices including a so-called ODT (On Die Termination) function (see Japanese Patent Application Laid-open No. 2008-060641). The ODT function is a function for using a data input/output terminal provided in a semiconductor device as a terminating resistor. Using the ODT function, it is possible to prevent a degradation of signal quality due to a reflection of the signal at the end of a transmission line, without mounting a terminating resistor on a mounting board. In a semiconductor device having the ODT function, an ODT operation is performed in synchronization with an internal clock, and therefore the DLL circuit is required to operate also at the time of the ODT operation.
However, the operation margin of the data input/output circuit with respect to the external clock is larger at the time of the ODT operation than at the time of the read operation. In other words, while tolerance of mismatch is relatively small in the phases of the read data and the external clock, the tolerance is relatively large in the phases of the operation timing of the ODT circuit and the external clock. This means that the operation timing of the ODT circuit does not require control as strict as that for the output timing of read data, which is also defined in the specifications. The present inventor focused his attention on this point, and performed a thorough examination to reduce the power consumption of the DLL circuit.
The problem described above is not only a problem in a synchronous memory device that includes a DLL circuit but also a common problem to all semiconductor devices that include other types of clock generating circuits.